1. Field of the Invention
The present invention relates to a method for producing a semiconductor device by charged-particle beam exposure using a character projection (CP) method and a system for producing the semiconductor device.
2. Description of the Related Art
Electron-beam exposure is an effective means for processing a fine pattern of a semiconductor circuit.
In a variable shaped beam (VSB) method that is a typical electron-beam exposure method, a circuit pattern is divided into very small rectangles and triangles and these are repeatedly exposed to an electron beam. It is thus unnecessary to prepare a mask dedicated to the exposure of the pattern. However, a very large number of shots of the electron beam are required and thus a reduction in throughput is inevitable.
A character projection (CP) method is contrived in order to improve the throughput of the VSB method. In the CP method, the charged-particle beam is formed to characters within a maximum size of the beam. The characters are exposed by the electron beam at once, thereby reducing the number of shots of the beam and improving the throughput. The electron beam is formed by a character-shaped CP aperture. In a commonly used electron-beam exposure apparatus, the number of apertures that can be formed in a deflection region of a character-selecting deflector is 100 at the most. In a device which has a number of same patterns which is used repeatedly such as a memory, most of the patterns can be exposed by the CP method. In a logic device such as an ASIC (application-specific integrated circuit), the number of types of characters used repeatedly is as large as several hundreds to several thousands. The VSB method is therefore used more frequently than the CP method to expose the characters. If the VSB method increases in use, the effect of reducing the number of shots, which is created by adopting the CP method, is lessened naturally; therefore, a high throughput cannot be achieved. Since a CP aperture is required for each product, manufacturing costs cannot be decreased, nor can be time periods.
In producing a logic device as described above, especially a circuit pattern designed on the basis of standard cells (SC), a logic synthesis method and an P & R (Place and Route) method are proposed, which greatly reduces the number of standard cells (SC) serving as characters when electron-beam exposure is performed by the CP method or the number of standard cells for use is restricted. According to these methods, the performance of the circuit pattern slightly deteriorates and the area of a chip does not decrease. However, the number of shots of electron-beam exposure can be reduced and the number of characters for exposure of the CP method can be made equal to or smaller than that of characters, which can be prepared by an exposure apparatus. The same CP aperture can be used for different logic devices. A mask or a CP aperture need not be produced for each product, with the result that manufacturing costs and periods can be decreased.
According to the above design method, a plurality of patterns can be generated for desired device specifications. The most desirable pattern can thus be selected in terms of costs, delivery times, and capabilities. For example, the following five conditions are provided as pattern selection criteria in this case:
1) The number of shots of electron beam is the smallest or the throughput of exposure is the highest.
2) Electron beam exposure is performed using a previously formed CP aperture.
3) The chip area of a device to be manufactured is the smallest.
4) The power consumption of a device to be manufactured is the lowest.
5) The operating frequency of a device to be manufactured is the highest.
It is preferable that a person who makes a request to manufacture a device, i.e., a user or a customer of a semiconductor manufacturer decides which condition is prioritized and a logic device of what circuit pattern is produced.
A conventional process from the design of a circuit pattern of a semiconductor device to the electron-beam exposure of the circuit pattern will now be described with reference to the flowchart shown in FIG. 1.
As FIG. 1 shows, an electronic circuit of the semiconductor device is described first (s101). It is usually described using hardware description language (HDL). In particular, register transfer level (RTL) is employed to describe the arrangement and operation of registers and those of register-to-register logic circuits.
Then, logic synthesis is performed based on device characteristics such as the RTL and an operating frequency and design limiting conditions such as a chip area (s102). A logic circuit satisfying the design limiting conditions can thus be obtained. A circuit pattern is formed on the basis of the logic circuit. A functional unit such as a logic gate and a flip-flop is assigned to standard cells for optimizing a circuit pattern. These standard cells are arranged on a chip and connected to each other by wiring. This arrangement is called P & R (Place and Route).
After that, various verifications are performed to generate pattern data of the device (s103).
The above steps s101 to s103 are carried out by a designer of the circuit pattern. The step s104 and its subsequent steps are performed by a process engineer as follows.
First, an operator receives pattern data from the designer of the circuit pattern (s104) and extracts figures, which serves as characters for CP exposure or is used repeatedly, from the figures contained in the pattern data. The extracted figures is assigned to the characters for CP exposure, while the number of characters mountable on an exposure apparatus is set as a limit value (s105). The other figures is exposed by the VSB method.
A CP aperture is prepared for the characters to which the figures is assigned (s106). Based on information of steps s104 and s105, design information is converted to exposure data that can be put to an electron-beam exposure apparatus using pattern data (s107). The CP aperture formed in step s106 is attached to the exposure apparatus. The exposure data generated in step s107 is input to the exposure apparatus, and a sample coated with resist for processing is exposed to an electron beam (s108). The completely exposed sample is removed from the exposure apparatus and then heated and developed to form a resist pattern (s109).
In the foregoing techniques of designing a circuit pattern and exposing the pattern to an electron beam, the steps s101 to s103 are usually carried out by a designer of the circuit pattern, while the steps s104 to s109 are performed by a process engineer. It is not one person but a plurality of persons of different types who are in charge of the respective steps. The designer designs a circuit pattern without considering any characters in the electron-beam exposure of the CP method. On the other hand, the process engineer extracts figures as a unit of the CP exposure and assigns it to the characters. However, the designer cannot take into consideration all the contents that are subject to constraints in terms of a process. Consequently, the designer and engineer are satisfied with the parameters for the process and design, but they have no other choice but to take a very inefficient exposure method for the other parameters. This leads to the design and exposure method that do not necessarily meet the user's needs in manufacturing a semiconductor device. More specifically, when a user instructs a semiconductor-device maker to manufacture a semiconductor device performing a desired operation, the designer selects a circuit pattern that satisfies the optimum design condition based on the operation. Then, the process engineer makes the exposure device to expose the circuit pattern selected by the designer which is made by an electron beam. The above process therefore has the problem that the manufacturing costs and periods cannot meet the needs of a user. In other words, though the above five conditions 1) to 5) are provided as pattern selection criteria, the user's pattern selection is based on very limited parameters for design.